Multi-phase clocking is a competitive choice among clocking schemes for high-speed data links. It uses multiple phases of a low frequency clock that usually runs at a fraction of the full speed, which is the frequency of the data rate, to drive the input and output circuitries. As a compromise between speed and power consumption, multi-phase clocking helps achieve data rates in the gigabits range without stretching the frequency limits of clocking circuitries.
Unfortunately, multi-phase clocking has some unique problems. One example is clock phase error, which is defined as the difference in propagation delay between two phases accumulated through supposedly matched clock paths. Clock phase error is mainly caused by device and parasitic mismatch. There are wafer-to-wafer device mismatches and lot-to-lot device mismatches, but in general, two devices, even if manufactured to strict specifications, will never match perfectly because of the inherent error range attached to any manufacturing process. Parasitic mismatch, on the other hand, refers to the inherent capacitance associated with all devices and transmission lines. Both device mismatch and parasitic mismatch is relevant within any clocking scheme.
It is possible to correct clock phase error by adding an adjustable delay to the clock path. FIG. 1 shows a non-programmable differential-to-single-ended (D2SE) clock buffer that often is located at the end of a differential clock distribution path. The D2SE clock buffer converts a differential clock, such as a current-mode logic (CML) clock, to a full-rail clock that input/output (I/O) circuitries require.
FIG. 1 illustrates one embodiment of a standard non-programmable D2SE clock buffer. In FIG. 1, the pair of differential clock transmission lines enter the clock buffer circuit as inn (100) and inp (102). Each differential clock transmission line is coupled to the gate of an NMOS transistor, inn (100) is coupled to the gate of transistor 104 and inp (102) is coupled to the gate of transistor 106. In this embodiment of a standard D2SE clock buffer, two additional PMOS transistors (108 and 110) are present in the circuit. The layout of this clock buffer circuit allows the single-ended transmission line that begins at node outn1 (116) to alternately charge from a positive supply voltage (Vdd) when inn (100) is high and drain to a current drain Iss (112) when inp (102) is high. As soon as outn1 (116) has charged or drained enough, the inverter 114 will flip and send out the opposite signal on the single-ended clock transmission line (outp).
In this embodiment, it is assumed that the differential clock signal entering the D2SE clock buffer circuit from the inn (100) and inp (102) transmission lines has no clock-phase error and thus is aligned. As the signals make their way through the clock buffer circuit and eventually leave the circuit on outp they are potentially affected by any device and parasitic mismatch capacitances inherent to the circuit. Additionally, the clock buffer circuit is compensating for any error accumulated through the whole clock path. Thus, there may be a clock phase error when the differential clock converts to a single-ended clock at node outn1 (116). More specifically, the potential device mismatch of the capacitances for transistor 104 and transistor 106 may create a clock phase error. Also, the parasitic capacitance naturally within transistors 106 and 110 as well as within inverter 114 will create additional clock phase error at node outn1 (116).
FIG. 2 illustrates one embodiment of a limited solution added to the D2SE clock buffer to eliminate the device and parasitic mismatch capacitances inherent to the clock buffer in FIG. 1. In FIG. 2, the entire D2SE clock buffer from the pair of differential clock transmission lines, which enter the clock buffer circuit as inn (200) and inp (202), to the node outn1 (212) is identical. Then at the node outn1 (212), where the differential clock signal converted to the single-ended clock signal through the charge and discharge functionality as described in FIG. 1, one or more capacitors are added to the single-ended clock transmission line (shown in bubble 214). To create a more manageable and modifiable environment, in one embodiment the capacitors are programmable. When drain and source voltages change between the voltage supply (Vdd) and the ground (Vss), the depletion layer in the capacitors within 214 are affected and, subsequently, their gate capacitance. Thus, in this embodiment, it is possible to increase or decrease the capacitance of each of the one or more added capacitors to adjust to affected gate capacitance as necessary.
Though, there is an inherent problem with the solution in FIG. 2 because the non-programmable portion of the capacitors' gate capacitance is significant, which becomes overhead capacitance. The overhead requires extra power to drive this extra capacitive loading to compensate.